Description of the rxstatem module (eth_rxstatem.v)
There is just one state machine used in the receive module of the Ethernet IP
core. This module is placed in the eth_rxstatem sub-module.
The state machine has six different states:
• Idle state
• Drop state
• Preamble state
• SFD (standard frame delimiter) state
• Data 0 state
• Data 1 state
==>State machine (SM) goes to the drop state (StateDrop) after the reset and
immediately after that to the idle state (StateIdle) because MRxDV is set to 0. As soon as there is a valid data available on the PHY’s data lines (MRxD), PHY
informs receiver about that by setting the MRxDV signal to one.
==> Normally receiver expects preamble at the beginning of each packet. Standard preamble is 7 byte long (0xee). After that a one-byte SFD (start frame delimiter) is expected (0xde). If we put this together, then sample 0xdeeeeeee is expected (LSB received first).
Because the Ethernet IP core can also accept packets that don’t have a standard 7-byte preamble but only the SFD, receiver’s SM waits for the first 0x5 nibble (it is not important whether this nibble is part of the preamble or of the SFD).
If the received character differs from the expected nibble, then the SM goes to the preamble state (StatePreamble) and remains there until the correct nibble (0x5) is received. Once the 0x5 nibble is received, SM goes to the SFD state (StateSFD) where it waits for the 0xd nibble.
From here two things, depending on the value of the IFGCounterEq24 signal,may occur (next paragraph describes IFGCounterEq24 signal). If
IFGCounterEq24 is set then
1. SM goes to the data0 state (StateData0) where lower data nibble is
received and then to the data1 state (StateData1) where higher data
nibble is received. SM goes back to the data0 state. SM continues going
from data state 0 to data state 1 and vice versa until whole data packet is
received and end of packet is detected (PHY clears the MRxDV signal).
Once the data valid signal is cleared, SM goes to the idle state (StateIdle)
and everything starts again.
else (IFGCounterEq24 is cleared)
2. SM goes to the drop state (StateDrop) and remains there until the end of
valid data is reported (PHY clears the MRxDV signal). After that SM goes
to the idle state (StateIdle) and everything starts again.
Signal IFGCounterEq24 is used for detecting the proper gap between two
consecutive received frames (Inter Frame Gap). By the standard this gap must be at least 960 ns for 100 Mbps mode or 9600ns for 10 Mbps mode. If the gap is appropriate (equal or greater than requested), then IFGCounterEq24 is set to 1. Signal IFGCounterEq24 is also set to 1, when IFG bit in the MODER register is set (minimum inter frame gap is not checked). If the IFG gap between two frames is too small, frame won’t be accepted but dropped.
There is just one state machine used in the receive module of the Ethernet IP
core. This module is placed in the eth_rxstatem sub-module.
The state machine has six different states:
• Idle state
• Drop state
• Preamble state
• SFD (standard frame delimiter) state
• Data 0 state
• Data 1 state
==>State machine (SM) goes to the drop state (StateDrop) after the reset and
immediately after that to the idle state (StateIdle) because MRxDV is set to 0. As soon as there is a valid data available on the PHY’s data lines (MRxD), PHY
informs receiver about that by setting the MRxDV signal to one.
==> Normally receiver expects preamble at the beginning of each packet. Standard preamble is 7 byte long (0xee). After that a one-byte SFD (start frame delimiter) is expected (0xde). If we put this together, then sample 0xdeeeeeee is expected (LSB received first).
Because the Ethernet IP core can also accept packets that don’t have a standard 7-byte preamble but only the SFD, receiver’s SM waits for the first 0x5 nibble (it is not important whether this nibble is part of the preamble or of the SFD).
If the received character differs from the expected nibble, then the SM goes to the preamble state (StatePreamble) and remains there until the correct nibble (0x5) is received. Once the 0x5 nibble is received, SM goes to the SFD state (StateSFD) where it waits for the 0xd nibble.
From here two things, depending on the value of the IFGCounterEq24 signal,may occur (next paragraph describes IFGCounterEq24 signal). If
IFGCounterEq24 is set then
1. SM goes to the data0 state (StateData0) where lower data nibble is
received and then to the data1 state (StateData1) where higher data
nibble is received. SM goes back to the data0 state. SM continues going
from data state 0 to data state 1 and vice versa until whole data packet is
received and end of packet is detected (PHY clears the MRxDV signal).
Once the data valid signal is cleared, SM goes to the idle state (StateIdle)
and everything starts again.
else (IFGCounterEq24 is cleared)
2. SM goes to the drop state (StateDrop) and remains there until the end of
valid data is reported (PHY clears the MRxDV signal). After that SM goes
to the idle state (StateIdle) and everything starts again.
Signal IFGCounterEq24 is used for detecting the proper gap between two
consecutive received frames (Inter Frame Gap). By the standard this gap must be at least 960 ns for 100 Mbps mode or 9600ns for 10 Mbps mode. If the gap is appropriate (equal or greater than requested), then IFGCounterEq24 is set to 1. Signal IFGCounterEq24 is also set to 1, when IFG bit in the MODER register is set (minimum inter frame gap is not checked). If the IFG gap between two frames is too small, frame won’t be accepted but dropped.
No comments:
Post a Comment