MII module of ethernet (Media Independent Interface Moduel)

Media Independent Interface Moduel (MII)

• The MII module is the top module for the MII and consists of several sub modules
  (eth_clockgen.v, eth_shiftreg.v, eth_outputcontrol.v) and additional logic.
  This logic is used for generating number of signals:

1.  Synchronized request for write (WriteDataOp), read (ReadStatusOp)
   and scan (ScanStatusOp) operations.
2.  Signal for updating the MIIRX_DATA register (UpdateMIIRX_DATAReg)
    Counter (BitCounter) is the primary counter for the MII Interface (many
   operations depend on it.
3. Byte select signals used when data is shifted out (ByteSelect [3:0]).
4.  Signals used for latching the input data (LatchByte [1:0]).

Performing Read/Write using MII Interface: 

  When there is a need to read or write the data from the PHY chip, several
operations need to be performed:

 1. MIIMODER register needs to be set:

1. Clock divider needs to be set to provide clock signal Mdc of the       appropriate frequency (read PHY documentation to obtain the value of the Mdc frequency)
2. Preamble generation might be disabled (if PHY supports transmissions without the preamble). By default 32-bit preamble is transmitted.
3. MII Module might be reset prior to its usage.

2. PHY Address (several PHY chips might be connected to the MII interface)
    and address of the register within the selected PHY chip need to be set in
    the MIIADDRESS register.
3. If there is a need to write data to the selected register, data needs to be
    written to the MIITX_DATA register.
4. Writing appropriate value to the MIICOMMAND register starts requested
    operation.
5.  If “Read status” or ”Scan status” operation were requested than the value
     that was received from the PHY can be read from the MIIRX_DATA
     register.
6.  MIISTATUS register reflects the status of the MII module. The LinkFail   status is cleared only after the read to the PHY’s status register (address 0x1)  returns status that is OK.

sub_module1. Description of the eth_outputcontrol module

This module performs two tasks:
  1. Generates MII serial output signal (Mdo)
  2. Generates enable signal (MdoEn) for the Mdo.

Since the MII serial data signal is a bi-directional signal, these two signals
need to be combined together with the MII serial input signal (Mdi) in
additional module that is not part of the Ethernet MAC IP Core.
The eth_outputcontrol module also generates the MII preamble. When MII
preamble is enabled (bit 8 in the MIIMODER register set to 0), 32-bit
preamble is transmitted prior to the data.

sub_module2. Description of the eth_clockgen module

The eth_clockgen module is used for:
  1.  Generating MII clock signal (Mdc). This is output clock signal used for
       clocking the MII interface of the Ethernet PHY chip. You should read the
       specification for the used PHY chip to properly set the Mdc frequency
       (usually frequencies up to 10 MHz can be used)
  2. Generating MdcEn signal. This signal is an enable signal. All flip-flops
      used in the MII are clocked with the high frequency clock Clk. The
      reduced frequency (equal to Mdc) is obtained by using the MdcEn signal.
      Mdc is obtained by dividing the Clk signal with the value that is written in the MIIMODER register (any value within range [1:255]).

sub_module3. Description of the eth_shiftreg module

The eth_shiftreg module is used for:
  1.  Serialize the data that goes towards Ethernet PHY chip (Mdo)
  2.  Parallelize input data that comes from Ethernet PHY chip (Mdi) and
       temporally store it to the Prsd register. This value is then stored to the
       MIIRX_DATA register.
 3.  Generating LinkFail signal (bit 0 of the MIISTATUS register reflects its
      value).