Description of the Receive module (eth_rxethmac.v)
The Receive module is in charge for receiving data. External PHY chip receives serial data from the physical layer (cable), assembles it to nibbles and sends to the receive module (MRxD [3:0]) together with the “data valid” marker (MRxDV).
The receive module then assembles this data nibbles to data bytes, and sends them to the WISHBONE interface module together with few signals that mark start and end of the data. Receive module also removes the preamble and the CRC.
The Receive module consists of four sub modules:
• eth_crc – Cyclic Redundancy Check (CRC) module
• eth_rxaddrcheck – Address recognition module
• eth_rxcounters – Various counters needed for packet reception
• eth_rxstatem – State machine for Receive module
Besides the above sub modules, eth_rxethmac module also consists of logic that is used for:
1. Generating CrcHash value and CrcHashGood marker that are used in
address recognition system.
2. Latching the data that is received from the PHY chip (RxData).
3. Generating Broadcast and Multicast marker (when packets with
broadcast or multicast destination address are received).
4. Generating RxValid, RxStartFrm, RxEndFrm signals that are marking
valid data.
Receiver can operate in various modes. For that reason number of registers
need to be configured prior to Receiver’s use.
Signals related to the receiver operation are:
1. HugEn – Reception of big packets is enabled (packets, bigger than the
standard Ethernet packets). When HugEn is disabled, packets that
smaller or equal to MaxFL and bigger or equal to MinFL are received.
(MaxFL and MinFL are set in the PACKETLEN register).
2. DlyCrcEn – Delayed CRC (Cyclic Redundancy Check) is enabled. CRC
checking starts 4 bytes after the data becomes valid. This option is useful
when additional data is added to the data frame.
3 . r_IFG – Minimum Inter Frame Gap Enable. When this signal is set to
zero, minimum inter frame gap is required between two packets. After this
time receiver starts with reception again. When r_IFG is set to 1, no inter
packet gap is needed. All frames are received regardless to the IFG.
4. r_Pro, r_Bro, r_Iam and registers MAC, HASH0 and HASH1 are used
for address recognition.
Description of the rxcounters module (eth_rxcounters.v)
The module consists of three main counters, which are:
1. ByteCnt – generally used counter in the receive module.
2. IFGCounter – used for counting the IFG (inter frame gap)
3. DlyCrcCnt – counter, used when delayed CRC operation is enabled.
The Receive module is in charge for receiving data. External PHY chip receives serial data from the physical layer (cable), assembles it to nibbles and sends to the receive module (MRxD [3:0]) together with the “data valid” marker (MRxDV).
The receive module then assembles this data nibbles to data bytes, and sends them to the WISHBONE interface module together with few signals that mark start and end of the data. Receive module also removes the preamble and the CRC.
The Receive module consists of four sub modules:
• eth_crc – Cyclic Redundancy Check (CRC) module
• eth_rxaddrcheck – Address recognition module
• eth_rxcounters – Various counters needed for packet reception
• eth_rxstatem – State machine for Receive module
Besides the above sub modules, eth_rxethmac module also consists of logic that is used for:
1. Generating CrcHash value and CrcHashGood marker that are used in
address recognition system.
2. Latching the data that is received from the PHY chip (RxData).
3. Generating Broadcast and Multicast marker (when packets with
broadcast or multicast destination address are received).
4. Generating RxValid, RxStartFrm, RxEndFrm signals that are marking
valid data.
Receiver can operate in various modes. For that reason number of registers
need to be configured prior to Receiver’s use.
Signals related to the receiver operation are:
1. HugEn – Reception of big packets is enabled (packets, bigger than the
standard Ethernet packets). When HugEn is disabled, packets that
smaller or equal to MaxFL and bigger or equal to MinFL are received.
(MaxFL and MinFL are set in the PACKETLEN register).
2. DlyCrcEn – Delayed CRC (Cyclic Redundancy Check) is enabled. CRC
checking starts 4 bytes after the data becomes valid. This option is useful
when additional data is added to the data frame.
3 . r_IFG – Minimum Inter Frame Gap Enable. When this signal is set to
zero, minimum inter frame gap is required between two packets. After this
time receiver starts with reception again. When r_IFG is set to 1, no inter
packet gap is needed. All frames are received regardless to the IFG.
4. r_Pro, r_Bro, r_Iam and registers MAC, HASH0 and HASH1 are used
for address recognition.
Description of the rxcounters module (eth_rxcounters.v)
The module consists of three main counters, which are:
1. ByteCnt – generally used counter in the receive module.
2. IFGCounter – used for counting the IFG (inter frame gap)
3. DlyCrcCnt – counter, used when delayed CRC operation is enabled.
No comments:
Post a Comment