The TX module has one general state machine. This state machine has eleven states:
• StateIdle
• StatePreamble
• StateData0
• StateData1
• StatePAD
• StateFCS
• StateIPG
• StateJam
• StateJam_q
• StateBackOff
• StateDefer
After the reset defer state (StateDefer) is activated. After that the state machine goes to the “Inter Packet Gap” state (StateIPG) and then to the idle state (StateIdle). Why this is so, is not important at the moment.
Wishbone Interface (WBI) requests the transmission by setting the TxStartFrm signal to 1 for two clock cycles (together with the first byte of the data that needs to be sent). This forces the state machine (SM) to go to the preamble state (StatePreamble) from idle (StateIdle).
In the preamble state MTxEn signal is set to 1, informing the Ethernet PHY chip that transmission will start. Together with the MTxEn signal, data signal MTxD is set to the preamble value 0x5. After the preamble is sent (0x5555555), SFD is sent (Start Frame Delimiter (0xd)). After that SM goes to the data0 state (StateData0) and signal TxUsedData is set to inform the WBI to provide next data byte. LSB nibble of the data byte is sent and then SM goes to the data1 state (StateData1), where the MSB nibble of the data byte is sent. SM continues to switch between the data0 and data1 states until the end of the packet. When there is just one byte left to be send, WBI sets the signal TxEndFrm that marks the last byte of the data that needs to be sent.
From here, there are several possibilities:
1. If the data length is greater or equal to the minimum frame length (value
written in the MINFL field of the PACKETLEN register) and CRC is
enabled (bit CRCEN in the MODER register is set to 1 or bit CRC of the
transmit descriptor is set to 1) then SM goes to the StateFCS state where
the 32-bit CRC value, calculated from the data, is appended. Then the SM
goes to the defer state (StateDefer), then to the “Inter Packet Gap” state
(StateIPG) and from there to the idle state (StateIdle) where everything
starts again.
2. If the data length is greater or equal to the minimum frame length (value
written in the MINFL field of the PACKETLEN register) and CRC is
disabled (bit CRCEN in the MODER register is set to 0 and bit CRC of
the transmit descriptor is set to 0) then SM goes to the defer state
(StateDefer), then to the “Inter Packet Gap” state (StateIPG) and from
there to the idle state (StateIdle) where everything starts again.
3. If the data length is smaller than the minimum frame length (value written
in the MINFL field of the PACKETLEN register) and padding is enabled
(bit PAD in the MODER register is set to 1 or bit PAD of the transmit
descriptor is set to 1), then the SM goes to the pad state (StatePAD)
where data is padded with zeros until the minimum frame length is
achieved. Then the SM goes to the StateFCS state where the 32-bit CRC
value, calculated from the data, is appended. Then the SM goes to the
defer state (StateDefer), then to the “Inter Packet Gap” state (StateIPG)
and from there to the idle state (StateIdle) where everything starts again.
5. If the data length is smaller than the minimum frame length (value written
in the MINFL field of the PACKETLEN register), padding is disabled (bit
PAD in the MODER register is set to01 and bit PAD of the transmit
descriptor is set to 0) and CRC is enabled (bit CRCEN in the MODER
register is set to 1 or bit CRC of the transmit descriptor is set to 1) then the SM goes to the StateFCS state where the 32-bit CRC value, calculated
from the data, is appended. Then the SM goes to the defer state
(StateDefer), then to the “Inter Packet Gap” state (StateIPG) and from
there to the idle state (StateIdle) where everything starts again.
6. If the data length is smaller than the minimum frame length (value written
in the MINFL field of the PACKETLEN register), padding is disabled (bit
PAD in the MODER register is set to01 and bit PAD of the transmit
descriptor is set to 0) and CRC is disabled (bit CRCEN in the MODER
register is set to 0 and bit CRC of the transmit descriptor is set to 0) then
the SM goes to the defer state (StateDefer), then to the “Inter Packet
Gap” state (StateIPG) and from there to the idle state (StateIdle) where
everything starts again.
• StateIdle
• StatePreamble
• StateData0
• StateData1
• StatePAD
• StateFCS
• StateIPG
• StateJam
• StateJam_q
• StateBackOff
• StateDefer
After the reset defer state (StateDefer) is activated. After that the state machine goes to the “Inter Packet Gap” state (StateIPG) and then to the idle state (StateIdle). Why this is so, is not important at the moment.
Wishbone Interface (WBI) requests the transmission by setting the TxStartFrm signal to 1 for two clock cycles (together with the first byte of the data that needs to be sent). This forces the state machine (SM) to go to the preamble state (StatePreamble) from idle (StateIdle).
In the preamble state MTxEn signal is set to 1, informing the Ethernet PHY chip that transmission will start. Together with the MTxEn signal, data signal MTxD is set to the preamble value 0x5. After the preamble is sent (0x5555555), SFD is sent (Start Frame Delimiter (0xd)). After that SM goes to the data0 state (StateData0) and signal TxUsedData is set to inform the WBI to provide next data byte. LSB nibble of the data byte is sent and then SM goes to the data1 state (StateData1), where the MSB nibble of the data byte is sent. SM continues to switch between the data0 and data1 states until the end of the packet. When there is just one byte left to be send, WBI sets the signal TxEndFrm that marks the last byte of the data that needs to be sent.
From here, there are several possibilities:
1. If the data length is greater or equal to the minimum frame length (value
written in the MINFL field of the PACKETLEN register) and CRC is
enabled (bit CRCEN in the MODER register is set to 1 or bit CRC of the
transmit descriptor is set to 1) then SM goes to the StateFCS state where
the 32-bit CRC value, calculated from the data, is appended. Then the SM
goes to the defer state (StateDefer), then to the “Inter Packet Gap” state
(StateIPG) and from there to the idle state (StateIdle) where everything
starts again.
2. If the data length is greater or equal to the minimum frame length (value
written in the MINFL field of the PACKETLEN register) and CRC is
disabled (bit CRCEN in the MODER register is set to 0 and bit CRC of
the transmit descriptor is set to 0) then SM goes to the defer state
(StateDefer), then to the “Inter Packet Gap” state (StateIPG) and from
there to the idle state (StateIdle) where everything starts again.
3. If the data length is smaller than the minimum frame length (value written
in the MINFL field of the PACKETLEN register) and padding is enabled
(bit PAD in the MODER register is set to 1 or bit PAD of the transmit
descriptor is set to 1), then the SM goes to the pad state (StatePAD)
where data is padded with zeros until the minimum frame length is
achieved. Then the SM goes to the StateFCS state where the 32-bit CRC
value, calculated from the data, is appended. Then the SM goes to the
defer state (StateDefer), then to the “Inter Packet Gap” state (StateIPG)
and from there to the idle state (StateIdle) where everything starts again.
5. If the data length is smaller than the minimum frame length (value written
in the MINFL field of the PACKETLEN register), padding is disabled (bit
PAD in the MODER register is set to01 and bit PAD of the transmit
descriptor is set to 0) and CRC is enabled (bit CRCEN in the MODER
register is set to 1 or bit CRC of the transmit descriptor is set to 1) then the SM goes to the StateFCS state where the 32-bit CRC value, calculated
from the data, is appended. Then the SM goes to the defer state
(StateDefer), then to the “Inter Packet Gap” state (StateIPG) and from
there to the idle state (StateIdle) where everything starts again.
6. If the data length is smaller than the minimum frame length (value written
in the MINFL field of the PACKETLEN register), padding is disabled (bit
PAD in the MODER register is set to01 and bit PAD of the transmit
descriptor is set to 0) and CRC is disabled (bit CRCEN in the MODER
register is set to 0 and bit CRC of the transmit descriptor is set to 0) then
the SM goes to the defer state (StateDefer), then to the “Inter Packet
Gap” state (StateIPG) and from there to the idle state (StateIdle) where
everything starts again.
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